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cy8c24123a cy8c24223a cy8c24423a psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-12028 rev. *r revised april 24, 2012 psoc ? programmable system-on-chip features powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? 8 8 multiply, 32-bit accumulate ? low power at high speed ? operating voltage: 2.4 v to 5.25 v ? operating voltages down to 1. 0 v using on-chip switch mode pump (smp) ? industrial temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? six rail-to-rail analog psoc blocks provide: ? up to 14-bit analog-to-digital converters (adcs) ? up to 9-bit digital-to-analog converters (dacs) ? programmable gain amplifiers (pgas) ? programmable filters and comparators ? four digital psoc blocks provide: ? 8- to 32-bit timers and count ers, 8- and 16-bit pulse-width modulators (pwms) ? cyclical redundancy check (crc) and pseudo random sequence (prs) modules ? full-duplex universal asynchro nous receiver transmitter (uart) ? multiple serial peripheral interface (spi) masters or slaves ? can connect to all general-purpose i/o (gpio) pins ? complex peripherals by combining blocks precision, programmable clocking ? internal 2.5% 24- / 48-mhz main oscillator ? high accuracy 24 mhz with optional 32 khz crystal and phase-locked loop (pll) ? optional external oscillator up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 4 kb flash program storage 50,000 erase/write cycles ? 256-bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? electronically erasable programmable read only memory (eeprom) emulation in flash programmable pin configurations ? 25-ma sink, 10-ma source on all gpios ? pull-up, pull-down, high z, strong, or open-drain drive modes on all gpios ? eight standard analog inputs on all gpios, and four additional analog inputs with restricted routing ? two 30 ma analog outputs on all gpios ? configurable interrupt on all gpios new cy8c24x23a psoc device ? derived from the cy8c24x23 device ? low power and low voltage (2.4 v) additional system resources ? i 2 c slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured, in-cir cuit emulator (ice ), and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory digital system sram 256 bytes interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 4kb digital block array multiply accum. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref analog input muxing i 2 c port 2 port 1 port 0 analog drivers system bus analog block array logic block diagram
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 2 of 65 contents psoc functional overview .............................................. 3 psoc core .................................................................. 3 digital system ............................................................. 3 analog system ............................................................ 4 additional system resources ..................................... 5 psoc device characteristics . ..................................... 5 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules .............................................. 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 8-pin part pinout ......................................................... 8 20-pin part pinout ....................................................... 9 28-pin part pinout ..................................................... 10 32-pin part pinout ................................................... 11 56-pin part pinout ..................................................... 12 register reference ......................................................... 13 register conventions ................................................ 13 register mapping tables .......................................... 13 electrical specifications ................................................ 16 absolute maximum ratings ... .................................... 16 operating temperature ............................................ 17 dc electrical characteristics ..................................... 17 ac electrical characteristics ..................................... 34 packaging information ................................................... 47 packaging dimensions .............................................. 47 thermal impedances ................................................ 53 capacitance on crystal pins .............. .............. ........ 53 solder reflow specifications ..................................... 53 development tool selection .. .............. .............. ........... 54 software .................................................................... 54 development kits ...................................................... 54 evaluation tools ........................................................ 54 device programmers ............. .................................... 55 accessories (emulation and programming) .............. 55 ordering information ...................................................... 56 ordering code definitions ..... .................................... 56 acronyms ........................................................................ 57 acronyms used ......................................................... 57 reference documents .................................................... 57 document conventions ................................................. 58 units of measure ....................................................... 58 numeric conventions ............ .................................... 58 glossary .......................................................................... 58 document history page ................................................. 63 sales, solutions, and legal information ...................... 65 worldwide sales and design s upport ......... .............. 65 products .................................................................... 65 psoc solutions ......................................................... 65
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 3 of 65 psoc functional overview the psoc family consists of many programmable system-on-chips with on-chip cont roller devices. these devices are designed to replace multiple traditional mcu-based system components with a low-cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, and programmable interconnects. this architecture makes it possible for you to create customized perip heral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, shown in figure 1 , consists of four main areas: psoc core, digital syst em, analog system, and system resources. configurable global busing allows combining all the device resources into a comp lete custom system. the psoc cy8c24x23a family can have up to three i/o ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpios. the m8c cpu core is a powerful processor with speeds up to 24 hz, providing a four-mips 8-bit harvard-architecture microprocessor. the cpu uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watchdog timers (wdt). memory encompasses 4 kb of flash for program storage, 256 bytes of sram for data storage, and up to 2 kb of eeprom emulated using the flash. progra m flash uses four protection levels on blocks of 64 bytes, a llowing customized software ip protection. the psoc device incorporates flex ible internal clock generators, including a 24 mhz internal main oscillator (imo) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is required, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing gr eat flexibility in external interfacing. every pin can gener ate a system interrupt on high level, low level, and change from last read. digital system the digital system consists of four digital psoc blocks. each block is an 8-bit resource that may be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user module references. figure 1. digital system block diagram digital peripheral configurations are: pwms (8- and 16-bit) pwms with dead band (8- and 16-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8-bit with selectable parity spi master and slave i 2 c slave and multi-master (one is available as a system resource) crc generator (8- to 32-bit) irda prs generators (8- to 32-bit) the digital blocks may be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device fa mily. this gives a choice of system resources for your applic ation. family resources are shown in table 1 on page 5 . digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 2 port 1 port 0
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 4 of 65 analog system the analog system consists of six configurable blocks, each consisting of an opamp circuit that allows the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: adcs (up to two, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) filters (two and four pole band -pass, low-pass, and notch) amplifiers (up to two, with selectable gain to 48x) instrumentation amplifiers (one with selectable gain to 93x) comparators (up to two, with 16 selectable thresholds) dacs (up to two, with 6 to 9-bit resolution) multiplying dacs (up to two, with 6 to 9-bit resolution) high current output drivers (two with 30 ma drive as a psoc core resource) 1.3 v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in figure 2 figure 2. analog system block diagram acb00 acb01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 5 of 65 additional system resources system resources, some of whic h are listed in the previous sections, provide additional ca pability useful to complete systems. additional resources include a multiplier, decimator, switch-mode pump, low-voltage detection, and power-on-reset (por). statements describi ng the merits of each system resource follow: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks may be generated using di gital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i 2 c module provides 100- and 400-khz communication over two wires. slave, master, and multi-master are supported. low-voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.3 v reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch-mode pump generates normal operating voltages from a single 1.2 v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characterist ics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, o r 4 analog blocks. table 1 on page 5 lists the resources available for specific psoc device groups. the psoc device covered by this datasheet is highlighted in this table. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [1] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 up to 38 2 8 up to 38 0 4 6 [1] 1 k 16 k cy8c21x45 up to 24 1 4 up to 24 0 4 6 [1] 512 8 k cy8c21x34 up to 28 1 4 up to 28 0 2 4 [1] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [1] 256 4 k cy8c20x34 up to 28 0 0 up to 28 0 0 3 [1,2] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [1,2] up to 2 k up to 32 k notes 1. limited analog functionality. 2. two analog blocks and one capsense ? .
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 6 of 65 getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a ba se device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can us e to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 7 of 65 debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays onl ine, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called ps oc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the param- eters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifi- cations. each datasheet describes the use of each user module parameter, and other information that you may need to success- fully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to -breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 8 of 65 pinouts this section describes, lists, and illustrates the cy8c24x23a psoc device pins and pinout configurations. every port pin (label ed with a ?p?) is capable of digital i/o. however, v ss , v dd , smp, and xres are not capable of digital i/o. 8-pin part pinout note 3. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. table 2. 8-pin pdip and soic pin no. type pin name description figure 3. cy8c24123a 8-pin psoc device digital analog 1 i/o i/o p0[5] analog column mux input and column output 2 i/o i/o p0[3] analog column mux input and column output 3 i/o p1[1] crystal input (xtalin), i 2 c serial clock (scl), issp-sclk [3] 4 power v ss ground connection 5 i/o p1[0] crystal output (xtalout), i 2 c serial data (sda), issp-sdata [3] 6 i/o i p0[2] analog column mux input 7 i/o i p0[4] analog column mux input 8 power v dd supply voltage legend : a = analog, i = input, and o = output. pdip soic 1 2 3 4 8 7 6 5 v dd p0[4], a, i p0[2], a, i p1[0], xtalout, i2c sda a, io, p0[5] a, io, p0[3] i2c scl, xtalin, p1[1] v ss
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 9 of 65 20-pin part pinout table 3. 20-pin pdip, ssop, and soic pin no. type pin name description figure 4. cy8c24223a 20-pin psoc device digital analog 1 i/o i p0[7] analog column mux input 2 i/o i/o p0[5] analog column mux input and column output 3 i/o i/o p0[3] analog column mux input and column output 4 i/o i p0[1] analog column mux input 5 power smp smp connection to external components required 6 i/o p1[7] i 2 c scl 7 i/o p1[5] i 2 c sda 8 i/o p1[3] 9 i/o p1[1] xtalin, i 2 c scl, issp-sclk [4] 10 power v ss ground connection. 11 i/o p1[0] xtalout, i 2 c sda, issp-sdata [4] 12 i/o p1[2] 13 i/o p1[4] optional external clock input (extclk) 14 i/o p1[6] 15 input xres active high external reset with internal pull-down 16 i/o i p0[0] analog column mux input 17 i/o i p0[2] analog column mux input 18 i/o i p0[4] analog column mux input 19 i/o i p0[6] analog column mux input 20 power v dd supply voltage leg end : a = analog, i = input, and o = output. a, i, p0[7] a, io, p0[5] a, io, p0[3] a, i, p0[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] v ss pdip ssop soic 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v dd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda note 4. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 10 of 65 28-pin part pinout table 4. 28-pin pdip, ssop, and soic pin no. type pin name description figure 5. cy8c24423a 28-pin psoc device digital analog 1 i/o i p0[7] analog column mux input 2 i/o i/o p0[5] analog column mux input and column output 3 i/o i/o p0[3] analog column mux input and column output 4 i/o i p0[1] analog column mux input 5 i/o p2[7] 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input 8 i/o i p2[1] direct switched capacitor block input 9 power smp smp connection to external components required 10 i/o p1[7] i 2 c scl 11 i/o p1[5] i 2 c sda 12 i/o p1[3] 13 i/o p1[1] xtalin, i 2 c scl, issp-sclk [5] 14 power v ss ground connection. 15 i/o p1[0] xtalout, i 2 c sda, issp-sdata [5] 16 i/o p1[2] 17 i/o p1[4] optional extclk 18 i/o p1[6] 19 input xres active high external reset with internal pull-down 20 i/o i p2[0] direct switched capacitor block input 21 i/o i p2[2] direct switched capacitor block input 22 i/o p2[4] external analog ground (agnd) 23 i/o p2[6] external voltage reference (v ref ) 24 i/o i p0[0] analog column mux input 25 i/o i p0[2] analog column mux input 26 i/o i p0[4] analog column mux input 27 i/o i p0[6] analog column mux input 28 power v dd supply voltage legend : a = analog, i = input, and o = output. a, i, p0[7] a, io, p0[5] a, io, p0[3] a, i, p0[1] p2[7] p2[5] a, i, p2[3] a, i, p2[1] smp i2cscl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] v ss v dd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i p2[6], external vref p2[4], external agnd p2[2], a, i p2[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda pdip ssop soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 note 5. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 11 of 65 32-pin part pinout notes 6. the center pad on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated and no t connected to any other signal. 7. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. table 5. 32-pin qfn [6] pin no. type pin name description figure 6. cy8c24423a 32-pin psoc device digital analog 1 i/o p2[7] 2 i/o p2[5] 3 i/o i p2[3] direct switched capacitor block input 4 i/o i p2[1] direct switched capacitor block input 5 power v ss ground connection 6 power smp smp connection to external components required 7 i/o p1[7] i 2 c scl 8 i/o p1[5] i 2 c sda 9 nc no connection. pin must be left floating 10 i/o p1[3] 11 i/o p1[1] xtalin, i 2 c scl, issp-sclk [7] 12 power v ss ground connection 13 i/o p1[0] xtalout, i 2 c sda, issp-sdata [7] 14 i/o p1[2] 15 i/o p1[4] optional extclk 16 nc no connection. pin must be left floating 17 i/o p1[6] 18 input xres active high external reset with internal pull-down 19 i/o i p2[0] direct switched capacitor block input 20 i/o i p2[2] direct switched capacitor block input 21 i/o p2[4] external agnd 22 i/o p2[6] external v ref 23 i/o i p0[0] analog column mux input 24 i/o i p0[2] analog column mux input 25 nc no connection. pin must be left floating 26 i/o i p0[4] analog column mux input 27 i/o i p0[6] analog column mux input 28 power v dd supply voltage 29 i/o i p0[7] analog column mux input 30 i/o i/o p0[5] analog column mux input and column output 31 i/o i/o p0[3] analog column mux input and column output 32 i/o i p0[1] analog column mux input legend : a = analog, i = input, and o = output. p2[7] p2[5] a, i, p2[3] a, i, p2[1] v ss smp qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 p0[1], a, i p0[3], a, io p0[5], a, io p0[7], a, i v dd p0[6], a, i p0[4], a, i nc i2c scl, p1[7] i2c sda, p1[5] p0[2], a, i p0[0], a, i xres p1[6] nc p1[3] i2c scl, xtalin, p1[1] v ss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] nc p2[6], external vref p2[4], external agnd p2[2], a, i p2[0], a, i
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 12 of 65 56-pin part pinout the 56-pin ssop part is for the cy8c24000a on-chip debug (ocd) psoc device. note this part is only used for in-circuit debugging. it is not available for production. table 6. 56-pin ssop ocd pin no. type pin name description figure 7. cy8c24000a 56-pin psoc device digital analog 1 nc no connection. pin must be left floating 2 i/o i p0[7] analog column mux input 3 i/o i p0[5] analog column mux input and column output 4 i/o i p0[3] analog column mux input and column output 5 i/o i p0[1] analog column mux input 6 i/o p2[7] 7 i/o p2[5] 8 i/o i p2[3] direct switched capacitor block input 9 i/o i p2[1] direct switched capacitor block input 10 nc no connection. pin must be left floating 11 nc no connection. pin must be left floating 12 nc no connection. pin must be left floating 13 nc no connection. pin must be left floating 14 ocd ocde ocd even data i/o 15 ocd ocdo ocd odd data output 16 power smp smp connection to required external compo- nents 17 nc no connection. pin must be left floating 18 nc no connection. pin must be left floating 19 nc no connection. pin must be left floating 20 nc no connection. pin must be left floating 21 nc no connection. pin must be left floating 22 nc no connection. pin must be left floating 23 i/o p1[7] i 2 c scl 24 i/o p1[5] i 2 c sda 25 nc no connection. pin must be left floating 26 i/o p1[3] 27 i/o p1[1] xtalin, i 2 c scl, issp-sclk [8] 28 power v dd supply voltage 29 nc no connection. pin must be left floating 30 nc no connection. pin must be left floating 31 i/o p1[0] xtalout, i 2 c sda, issp-sdata [8] 32 i/o p1[2] 33 i/o p1[4] optional extclk 34 i/o p1[6] 35 nc no connection. pin must be left floating 36 nc no connection. pin must be left floating 37 nc no connection. pin must be left floating 38 nc no connection. pin must be left floating 39 nc no connection. pin must be left floating 40 nc no connection. pin must be left floating 41 input xres active high external reset with internal pull-down. 42 ocd hclk ocd high speed clock output. 43 ocd cclk ocd cpu clock output. 44 nc no connection. pin must be left floating 45 nc no connection. pin must be left floating 46 nc no connection. pin must be left floating 47 nc no connection. pin must be left floating 48 i/o i p2[0] direct switched capacitor block input. 49 i/o i p2[2] direct switched capacitor block input. 50 i/o p2[4] external agnd. 51 i/o p2[6] external v ref . 52 i/o i p0[0] analog column mux input. 53 i/o i p0[2] analog column mux input and column output. 54 i/o i p0[4] analog column mux input and column output. 55 i/o i p0[6] analog column mux input. 56 power v dd supply voltage. legend : a = analog, i = input, o = output, and ocd = on-chip debug. note 8. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. ssop 1 56 255 354 453 5 52 6 51 750 849 948 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 v dd p0[6], ai p0[4], aio p0[2], aio p0[0], ai p2[6], external vref p2[4], external agnd p2[2], ai p2[0], ai nc nc nc nc cclk hclk xres nc nc nc nc nc nc p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda, sdata nc nc ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[7] p2[5] ai, p2[3] ai, p2[1] nc nc nc nc ocde ocdo smp nc nc nc nc nc nc i2c scl, p1[7] i2c sda, p1[5] nc p1[3] sclk, i2c scl, xtalin, p1[1] v ss nc not for production
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 13 of 65 register reference this section lists the registers of the cy8c24x23a psoc device. for detailed register information, see the psoc programmable sytem-on-chip reference manual . register conventions abbreviations used the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is re ferred to as i/o space and is divided into two banks, bank 0 a nd bank 1. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set, the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 7. abbreviations convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 14 of 65 table 8. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 asd20cr0 90 rw d0 11 51 asd20cr1 91 rw d1 12 52 asd20cr2 92 rw d2 13 53 asd20cr3 93 rw d3 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw i2c_cfg d6 rw 17 57 asc21cr3 97 rw i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 a8 mul_x e8 w dcb02dr1 29 w 69 a9 mul_y e9 w dcb02dr2 2a rw 6a aa mul_dh ea r dcb02cr0 2b # 6b ab mul_dl eb r dcb03dr0 2c # 6c ac acc_dr1 ec rw dcb03dr1 2d w 6d ad acc_dr0 ed rw dcb03dr2 2e rw 6e ae acc_dr3 ee rw dcb03cr0 2f # 6f af acc_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 15 of 65 table 0-1. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 asc10cr0 80 rw c0 prt0dm1 01 rw 41 asc10cr1 81 rw c1 prt0ic0 02 rw 42 asc10cr2 82 rw c2 prt0ic1 03 rw 43 asc10cr3 83 rw c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 asd20cr0 90 rw gdi_o_in d0 rw 11 51 asd20cr1 91 rw gdi_e_in d1 rw 12 52 asd20cr2 92 rw gdi_o_ou d2 rw 13 53 asd20cr3 93 rw gdi_e_ou d3 rw 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw d6 17 57 asc21cr3 97 rw d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw 6c ac ec dcb03in 2d rw 6d ad ed dcb03ou 2e rw 6e ae ee 2f 6f af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 16 of 65 electrical specifications this section presents the dc and ac electrical specifications of the cy8c24x23a psoc device. for the latest electrical specific ations, check if you have the most recent da tasheet by visiting the website at http://www.cypress.com . specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. refer to table 29 on page 34 for the electrical specificatio ns for the imo using slimo mode. absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 figure 8. voltage versus cpu frequency figure 8. imo frequency trim options table 9. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 65 c degrades reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 17 of 65 operating temperature dc electrical characteristics dc chip-level specifications ta b l e 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 10. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see table 48 on page 53 . you must limit the power consumption to comply with this requirement table 11. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 2.4 ? 5.25 v see dc por and lvd specifications, table 26 on page 32 i dd supply current ? 5 8 ma conditions are v dd = 5.0 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off slimo mode = 0. imo = 24 mhz i dd3 supply current ? 3.3 6.0 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz i dd27 supply current ? 2 4 ma conditions are v dd = 2.7 v, t a = 25 c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz, analog power = off. slimo mode = 1. imo = 6 mhz i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [9] ? 3 6.5 a conditions are with internal slow speed oscillator, v dd = 3.3 v, ?40 c ? t a ? 55 c, analog power = off i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [9] ? 4 25 a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 c < t a ? 85 c, analog power = off i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. [9] ? 4 7.5 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. v dd = 3.3 v, ?40 c ? t a ? 55 c, analog power = off i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. [9] ? 5 26 a conditions are with properly loaded, 1w max, 32.768 khz crystal. v dd = 3.3 v, 55 c < t a ? 85 c, analog power = off v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate v dd . v dd > 3.0 v v ref27 reference voltage (bandgap) 1.16 1.30 1.32 v trimmed for appropriate v dd . v dd = 2.4 v to 3.0 v note 9. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this must be compare d with devices that have similar functions enabled.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 18 of 65 dc gpio specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 12. 5-v and 3.3-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (maximum 40 ma on even port pins (for example, p0[2], p1[4]), maximum 40 ma on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (maximum 100 ma on even port pins (for example, p0[2], p1[4]), maximum 100 ma on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined i ol budget. i oh high level source current 10 ? ? ma v oh = v dd ? 1.0 v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v dd = 3.0 to 5.25 v ih input high level 2.1 ? v v dd = 3.0 to 5.25 v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c table 13. 2.7-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 0.4 ? ? v i oh = 2 ma (6.25 typ), v dd = 2.4 to 3.0 v (16 ma maximum, 50 ma typ combined i oh budget). v ol low output level ? ? 0.75 v i ol = 11.25 ma, v dd = 2.4 to 3.0 v (90 ma maximum combined i ol budget). i oh high level source current 2 ? ? ma v oh = v dd ? 0.4, see the limitations of total current in note for v oh . v il input low level ? ? 0.75 v v dd = 2.4 to 3.0 v ih input high level 2.0 ? ? v v dd = 2.4 to 3.0 v h input hysteresis ? 90 ? mv i ol low level sink current 11.25 ? ? ma v ol = .75, see the limitations of total current in note for v ol . i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 19 of 65 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog co ntinuous time psoc blocks and the analog switched cap psoc blocks . the guaranteed specifications are measured in the analog continuous time psoc block. typical parameters are measured at 5 v at 25 c and are for design guidance only. table 14. 5-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? v dd v dd ? 0.5 v the common mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? ? ? ? ? db db db specification is applicable at high opamp bias. for low opamp bias mode, minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high v dd ? 0.2 v dd ? 0.2 v dd ? 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? v in ?? (v dd ? 2.25) or (v dd ? 1.25 v) ?? v in ? v dd
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 20 of 65 table 15. 3.3-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 10 8 ? mv mv mv power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, ppamp opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? ? ? ? ? db db db specification is applicable at low opamp bias. for high opamp bias mode (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. v olowoa low output voltage swing (internal signals) power = low, ppamp opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? ? a ? a ? a ? a ? a ? a power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? v in ?? (v dd ? 2.25) or (v dd ? 1.25 v) ?? v in ? v dd
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 21 of 65 dc low power comparator specifications ta b l e 1 7 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v at 25 c and are for design guidance only. table 16. 2.7-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 10 8 ? mv mv mv power = high, opamp bias = high setting is not allowed for 2.7 v v dd operation. tcv osoa average input offset voltage drift ? 7.0 35.0 ? v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? ? ? ? ? db db db specification is applicable at low opamp bias. for high opamp bias mode, (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v power = high, opamp bias = high setting is not allowed for 2.7 v v dd operation. v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v power = high, opamp bias = high setting is not allowed for 2.7 v v dd operation. i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? ? a ? a ? a ? a ? a ? a power = high, opamp bias = high setting is not allowed for 2.7 v v dd operation. psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? v in ?? (v dd ? 2.25) or (v dd ? 1.25 v) ?? v in ? v dd table 17. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 22 of 65 dc analog output bu ffer specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 18. 5-v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 32 ohms to v dd/2 ) power = low power = high 0.5 v dd + 1.1 0.5 v dd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to v dd/2 ) power = low power = high ? ? ? ? .5 v dd ? 1.3 0.5 v dd ? 1.3 v v i sob supply current including opamp bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd ? 1.25) table 19. 3.3-v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1 k ohms to v dd/2 ) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1 k ohms to v dd/2 ) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v i sob supply current including opamp bias cell (no load) power = low power = high ? ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd ? 1.25)
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 23 of 65 dc switch mode pump specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 20. 2.7-v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1 k ohms to v dd/2 ) power = low power = high 0.5 v dd + 0.2 0.5 v dd + 0.2 ? ? ? ? v v v olowob low output voltage swing (load = 1 k ohms to v dd/2 ) power = low power = high ? ? ? ? 0.5 v dd ? 0.7 0.5 v dd ? 0.7 v v i sob supply current including opamp bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd ? 1.25). table 21. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5 v 5 v output voltage from pump 4.75 5.0 5.25 v configuration listed in footnote. [10] average, neglecting ripple. smp trip voltage is set to 5.0 v. v pump 3 v 3.3 v output voltage from pump 3.00 3.25 3.60 v configuration listed in footnote. [10] average, neglecting ripple. smp trip voltage is set to 3.25 v. v pump 2 v 2.6 v output voltage from pump 2.45 2.55 2.80 v configuration listed in footnote. [10] average, neglecting ripple. smp trip voltage is set to 2.55 v. i pump available output current v bat = 1.8 v, v pump = 5.0 v v bat = 1.5 v, v pump = 3.25 v v bat = 1.3 v, v pump = 2.55 v 5 8 8 ? ? ? ? ? ? ma ma ma configuration listed in footnote. [10] smp trip voltage is set to 5.0 v. smp trip voltage is set to 3.25 v. smp trip voltage is set to 2.55 v. v bat 5 v input voltage range from battery 1.8 ? 5.0 v configuration listed in footnote. [10] smp trip voltage is set to 5.0 v. v bat 3 v input voltage range from battery 1.0 ? 3.3 v configuration listed in footnote. [10] smp trip voltage is set to 3.25 v. v bat 2 v input voltage range from battery 1.0 ? 3.0 v configuration listed in footnote. [10] smp trip voltage is set to 2.55 v. note 10. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. see figure 9
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 24 of 65 figure 9. basic switch mode pump circuit v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration listed in footnote. [10] 0 c ? t a ? 100. 1.25 v at t a = ?40 c ? v pump_line line regulation (over v bat range) ?5 ?%v o configuration listed in footnote. [10] v o is the v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 26 on page 32 . ? v pump_load load regulation ? 5 ? %v o configuration listed in footnote. [10] v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 26 on page 32 . ? v pump_ripple output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configuration listed in footnote. [10] load is 5 ma. e 3 efficiency 35 50 ? % configuration listed in footnote. [10] load is 5 ma. smp trip voltage is set to 3.25 v. e 2 efficiency ? ? ? f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % table 21. dc switch mode pump (smp) specifications (continued) symbol description min typ max units notes battery c1 d1 + psoc vdd vss smp v bat l 1 v pump
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 25 of 65 dc analog reference specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. the guaranteed specifications for refhi an d reflo are measured through the analog continuous time psoc blocks. the power levels for refhi and reflo refer to the analog reference control register. agnd is measured at p2[4] in agnd bypass mode. each analog continuous time psoc block adds a maximum of 10 mv addi tional offset error to guaranteed agnd specifications from the local agnd buffer. reference control power can be set to medium or high unless otherwise noted. note avoid using p2[4] for digital signaling when using an analog resource that depends on the analog reference. some coupling of the digital signal may appear on the agnd. table 22. 5-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.136 v dd /2 + 1.288 v dd /2 + 1.409 v v agnd agnd v dd /2 v dd /2 ? 0.138 v dd /2 + 0.003 v dd /2 + 0.132 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.417 v dd /2 ? 1.289 v dd /2 ? 1.154 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.202 v dd /2 + 1.290 v dd /2 + 1.358 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 + 0.001 v dd /2 + 0.055 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.369 v dd /2 ? 1.295 v dd /2 ? 1.218 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.211 v dd /2 + 1.292 v dd /2 + 1.357 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 v dd /2 + 0.052 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.368 v dd /2 ? 1.298 v dd /2 ? 1.224 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.215 v dd /2 + 1.292 v dd /2 + 1.353 v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.033 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.368 v dd /2 ? 1.299 v dd /2 ? 1.225 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.076 p2[4] + p2[6] ? 0.021 p2[4] + p2[6] + 0.041 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.025 p2[4] ? p2[6] + 0.011 p2[4] ? p2[6] + 0.085 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.069 p2[4] + p2[6] ? 0.014 p2[4] + p2[6] + 0.043 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.029 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.052 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.072 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.048 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.057 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.009 p2[4] + p2[6] + 0.047 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.033 p2[4] ? p2[6] + 0.001 p2[4] ? p2[6] + 0.039 v
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 26 of 65 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.121 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 v dd /2 + 0.034 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.019 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.083 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.033 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.016 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.075 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.032 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.074 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.032 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.753 3.874 3.979 v v agnd agnd 2 bandgap 2.511 2.590 2.657 v v reflo ref low bandgap 1.243 1.297 1.333 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.767 3.881 3.974 v v agnd agnd 2 bandgap 2.518 2.592 2.652 v v reflo ref low bandgap 1.241 1.295 1.330 v refpower = medium opamp bias = high v refhi ref high 3 bandgap 2.771 3.885 3.979 v v agnd agnd 2 bandgap 2.521 2.593 2.649 v v reflo ref low bandgap 1.240 1.295 1.331 v refpower = medium opamp bias = low v refhi ref high 3 bandgap 3.771 3.887 3.977 v v agnd agnd 2 bandgap 2.522 2.594 2.648 v v reflo ref low bandgap 1.239 1.295 1.332 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.481 + p2[6] 2.569 + p2[6] 2.639 + p2[6] v v agnd agnd 2 bandgap 2.511 2.590 2.658 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.515 ? p2[6] 2.602 ? p2[6] 2.654 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.498 + p2[6] 2.579 + p2[6] 2.642 + p2[6] v v agnd agnd 2 bandgap 2.518 2.592 2.652 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.598 ? p2[6] 2.650 ? p2[6] v refpower = medium opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.504 + p2[6] 2.583 + p2[6] 2.646 + p2[6] v v agnd agnd 2 bandgap 2.521 2.592 2.650 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.596 ? p2[6] 2.649 ? p2[6] v refpower = medium opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.505 + p2[6] 2.586 + p2[6] 2.648 + p2[6] v v agnd agnd 2 bandgap 2.521 2.594 2.648 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.595 ? p2[6] 2.648 ? p2[6] v table 22. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 27 of 65 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.228 p2[4] + 1.284 p2[4] + 1.332 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.358 p2[4] ? 1.293 p2[4] ? 1.226 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.236 p2[4] + 1.289 p2[4] + 1.332 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.357 p2[4] ? 1.297 p2[4] ? 1.229 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.237 p2[4] + 1.291 p2[4] + 1.337 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.356 p2[4] ? 1.299 p2[4] ? 1.232 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.237 p2[4] + 1.292 p2[4] + 1.337 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.357 p2[4] ? 1.300 p2[4] ? 1.233 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.512 2.594 2.654 v v agnd agnd bandgap 1.250 1.303 1.346 v v reflo ref low v ss v ss v ss + 0.011 v ss + 0.027 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.515 2.592 2.654 v v agnd agnd bandgap 1.253 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.02 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.518 2.593 2.651 v v agnd agnd bandgap 1.254 1.301 1.338 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.517 2.594 2.650 v v agnd agnd bandgap 1.255 1.300 1.337 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.011 4.143 4.203 v v agnd agnd 1.6 bandgap 2.020 2.075 2.118 v v reflo ref low v ss v ss v ss + 0.011 v ss + 0.026 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.022 4.138 4.203 v v agnd agnd 1.6 bandgap 2.023 2.075 2.114 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 3.2 bandgap 4.026 4.141 4.207 v v agnd agnd 1.6 bandgap 2.024 2.075 2.114 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.015 v refpower = medium opamp bias = low v refhi ref high 3.2 bandgap 4.030 4.143 4.206 v v agnd agnd 1.6 bandgap 2.024 2.076 2.112 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.013 v table 22. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 28 of 65 table 23. 3.3-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.170 v dd /2 + 1.288 v dd /2 + 1.376 v v agnd agnd v dd /2 v dd /2 ? 0.098 v dd /2 + 0.003 v dd /2 + 0.097 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.386 v dd /2 ? 1.287 v dd /2 ? 1.169 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.210 v dd /2 + 1.290 v dd /2 + 1.355 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 + 0.001 v dd /2 + 0.054 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.359 v dd /2 ? 1.292 v dd /2 ? 1.214 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.198 v dd /2 + 1.292 v dd /2 + 1.368 v v agnd agnd v dd /2 v dd /2 ? 0.041 v dd /2 v dd /2 + 0.04 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.362 v dd /2 ? 1.295 v dd /2 ? 1.220 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.202 v dd /2 + 1.292 v dd /2 + 1.364 v v agnd agnd v dd /2 v dd /2 ? 0.033 v dd /2 v dd /2 + 0.030 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.364 v dd /2 ? 1.297 v dd /2 ? 1.222 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.072 p2[4] + p2[6] ? 0.017 p2[4] + p2[6] + 0.041 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.029 p2[4] ? p2[6] + 0.010 p2[4] ? p2[6] + 0.048 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.066 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.043 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.024 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.034 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.007 p2[4] + p2[6] + 0.053 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.028 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.033 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.056 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.030 p2[4] ? p2[6] p2[4] ? p2[6] + 0.032 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.102 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 + 0.001 v dd /2 + 0.039 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.020 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.082 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.031 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.083 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.032 v dd /2 ? 0.001 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.081 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.033 v dd /2 ? 0.001 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.013 v 0b011 all power settings not allowed at 3.3 v ??? ? ? ??
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 29 of 65 0b100 all power settings not allowed at 3.3 v ??? ? ? ?? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.211 p2[4] + 1.285 p2[4] + 1.348 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.354 p2[4] ? 1.290 p2[4] ? 1.197 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.209 p2[4] + 1.289 p2[4] + 1.353 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.352 p2[4] ? 1.294 p2[4] ? 1.222 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.218 p2[4] + 1.291 p2[4] + 1.351 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.351 p2[4] ? 1.296 p2[4] ? 1.224 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.215 p2[4] + 1.292 p2[4] + 1.354 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.352 p2[4] ? 1.297 p2[4] ? 1.227 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.460 2.594 2.695 v v agnd agnd bandgap 1.257 1.302 1.335 v v reflo ref low v ss v ss v ss + 0.01 v ss + 0.029 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.462 2.592 2.692 v v agnd agnd bandgap 1.256 1.301 1.332 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.473 2.593 2.682 v v agnd agnd bandgap 1.257 1.301 1.330 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.470 2.594 2.685 v v agnd agnd bandgap 1.256 1.300 1.332 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.012 v 0b111 all power settings not allowed at 3.3 v ??? ? ? ?? table 23. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 30 of 65 table 24. 2.7-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 all power settings not allowed at 2.7 v ??? ? ? ?? 0b001 refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.739 p2[4] + p2[6] ? 0.016 p2[4] + p2[6] + 0.759 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 1.675 p2[4] ? p2[6] + 0.013 p2[4] ? p2[6] + 1.825 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.098 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.067 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.308 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.362 v refpower = low opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.042 p2[4] + p2[6] ? 0.005 p2[4] + p2[6] + 0.035 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.030 p2[4] ? p2[6] p2[4] ? p2[6] + 0.030 v refpower = low opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.367 p2[4] + p2[6] ? 0.005 p2[4] + p2[6] + 0.308 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.345 p2[4] ? p2[6] p2[4] ? p2[6] + 0.301 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.100 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.038 v dd /2 v dd /2 + 0.036 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.016 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.065 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.025 v dd /2 v dd /2 + 0.023 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.012 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.054 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.024 v dd /2 ? 0.001 v dd /2 + 0.020 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.012 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.042 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.027 v dd /2 ? 0.001 v dd /2 + 0.022 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.010 v refpower = low opamp bias = high v refhi ref high v dd v dd ? 0.042 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 ? 0.001 v dd /2 + 0.023 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.010 v refpower = low opamp bias = low v refhi ref high v dd v dd ? 0.036 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.184 v dd /2 ? 0.001 v dd /2 + 0.159 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.009 v
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 31 of 65 dc analog psoc block specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. 0b011 all power settings not allowed at 2.7 v ??? ? ? ?? 0b100 all power settings not allowed at 2.7 v ??? ? ? ?? 0b101 all power settings not allowed at 2.7 v ??? ? ? ?? 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap not allowed not allowed not allowed v v agnd agnd bandgap 1.160 1.302 1.340 v v reflo ref low v ss v ss v ss + 0.007 v ss + 0.025 v refpower = high opamp bias = low v refhi ref high 2 bandgap not allowed not allowed not allowed v v agnd agnd bandgap 1.160 1.301 1.338 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 2 bandgap not allowed not allowed not allowed v v agnd agnd bandgap 1.160 1.301 1.338 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.013 v refpower = medium opamp bias = low v refhi ref high 2 bandgap not allowed not allowed not allowed v v agnd agnd bandgap 1.160 1.300 1.337 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.011 v refpower = low opamp bias = high v refhi ref high 2 bandgap not allowed not allowed not allowed v v agnd agnd bandgap 1.252 1.300 1.339 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.011 v refpower = low opamp bias = low v refhi ref high 2 bandgap not allowed not allowed not allowed v v agnd agnd bandgap 1.252 1.300 1.339 v v reflo ref low v ss v ss v ss + 0.001 v ss + 0.01 v 0b111 all power settings not allowed at 2.7 v ??? ? ? ?? table 24. 2.7-v dc analog reference specifications (continued) (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units table 25. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switched capacitor) ? 80 ? ff
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 32 of 65 dc por, smp, and lvd specifications ta b l e 2 3 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. note the bits porlev and vm in the following table refer to bits in the vlt_cr register. see the psoc programmable sytem-on-chip technical reference manual for more information on the vlt_cr register. table 26. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 0 2.92 0 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [11] 2.99 [12] 3.09 3.20 4.55 4.75 4.83 4.95 v 0 v 0 v 0 v 0 v 0 v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 v dd value for smp trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.50 0 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 0 3.02 3.10 3.25 0 4.64 4.73 4.82 5.00 2.62 [13] 3.09 3.16 3.32 [14] 4.74 4.83 4.92 5.12 v v 0 v 0 v 0 v 0 v v v notes 11. always greater than 50 mv above v ppor (porlev=00) for falling supply. 12. always greater than 50 mv above v ppor (porlev=01) for falling supply. 13. always greater than 50 mv above v lvd0 . 14. always greater than 50 mv above v lvd3 .
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 33 of 65 dc programming specifications ta b l e 2 7 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. dc i 2 c specifications ta b l e 2 8 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 27. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional require- ments of external programmer tools v ddlv low v dd for verify 2.4 2.5 2.6 v this specification applies to the functional require- ments of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional require- ments of external programmer tools v ddiwrite supply voltage for flash write operation 2.7 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 [15] ? ? ? erase/write cycles per block flash ent flash endurance (total) [16] 1,800,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years table 28. dc i 2 c specifications [17] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v ?? v dd ?? 3.6 v ? ? 0.25 v dd v 4.75 v ?? v dd ?? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v ?? v dd ?? 5.25 v notes 15. the 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. voltage ra nges are 2.4 v to 3.0 v, 3.0 v to 3.6 v, and 4.75 v to 5.25 v. 16. a maximum of 36 50,000 block endurance cycles is allowed. this may be balanced between operations on 36 1 blocks of 50,0 00 maximum cycles each, 36 2 blocks of 25,000 maximum cycles ea ch, or 36 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note design aids ? reading and writing psoc ? flash ? an2015 for more information. 17. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 34 of 65 ac electrical characteristics ac chip-level specifications these tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 29. 5-v and 3.3-v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator (imo) frequency for 24 mhz 23.4 24 24.6 [18,19] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 8 on page 16 . slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [18,19] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 8 on page 16 . slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.937 24 24.6 [18] mhz slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.937 12 12.3 [19] mhz slimo mode = 0. f 48m digital psoc block frequency 0 48 49.2 [18,20] mhz refer to the ac digital block specifications. f 24m digital psoc block frequency 0 24 24.6 [20] mhz f 32k1 ilo frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on timing this f pll pll frequency ? 23.986 ? mhz is a multiple (x732) of crystal frequency. t pllslew pll lock time 0.5 ? 10 ms t pllslewslow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 1700 2620 ms t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 w maximum drive level 32.768 khz crystal. 3.0 v ? v dd ? 5.5 v, ?40 c ? t a ? 85 c . t xrst external reset pulse width 10 ? ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [18,19] mhz trimmed. using factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . notes 18. 4.75 v < v dd < 5.25 v. 19. 3.0 v < v dd < 3.6 v. see application note adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 for information on trimming for operation at 3.3 v. 20. see the individual user module datasheets for information on maximum frequencies for user modules. 21. refer to cypress jitter specifications application note, understanding datasheet jitter specifications for cypress timing products ? an5054 for more information.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 35 of 65 t jit_imo [24] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps n = 32 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 ps 24 mhz imo period jitter (rms) ? 100 400 ps t jit_pll [24] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 800 ps n = 32 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 1200 24 mhz imo period jitter (rms) ? 100 700 table 30. 2.7-v ac chip-level specifications symbol description min typ max units notes f imo12 imo frequency for 12 mhz 11.5 12 12.7 [22,23] mhz trimmed for 2.7 v operation using factory trim values. see figure 8 on page 16 . slimo mode = 1. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [22,23] mhz trimmed for 2.7 v operation using factory trim values. see figure 8 on page 16 . slimo mode = 1. f cpu1 cpu frequency (2.7 v nominal) 0 0.937 0 3 0 3.15 [22] mhz 0 slimo mode = 0. f blk27 digital psoc block frequency (2.7 v nominal) 0 12 12.7 [22,23] mhz 0 refer to the ac digital block specifications. f 32k1 ilo frequency 8 32 96 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on timing this t xrst external reset pulse width 10 ? ? s dc12m 12 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % f max maximum frequency of signal on row input or row output. ? ? 12.7 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo [24] 12 mhz imo cycle-to-cycle jitter (rms) ? 400 1000 ps n = 32 12 mhz imo long term n cycle-to-cycle jitter (rms) ? 600 1300 ps 12 mhz imo period jitter (rms) ? 100 500 ps t jit_pll [24] 12 mhz imo cycle-to-cycle jitter (rms) ? 400 1000 ps n = 32 12 mhz imo long term n cycle-to-cycle jitter (rms) ? 700 1300 12 mhz imo period jitter (rms) ? 300 500 table 29. 5-v and 3.3-v ac chip-level specifications (continued) symbol description min typ max units notes notes 22. 2.4 v < v dd < 3.0 v. 23. refer to application note adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 for information on trimming for operation at 3.3 v. 24. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products ? an5054 for more information.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 36 of 65 figure 10. pll lock timing diagram figure 11. pll lock for low gain setting timing diagram figure 12. external crystal oscillator startup timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 37 of 65 ac gpio specifications these tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. figure 0-1. gpio timing diagram table 31. 5-v and 3.3-v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% to 90% table 32. 2.7-v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns v dd = 2.4 to 3.0 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns v dd = 2.4 to 3.0 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns v dd = 2.4 to 3.0 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns v dd = 2.4 to 3.0 v, 10% to 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 38 of 65 ac operational amplifier specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3 v and 2.7 v. table 33. 5-v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/s v/s v/s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/s v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 34. 3.3-v ac operatio nal amplifier specifications symbol description min typ max units t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/s v/s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 39 of 65 when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each bl ock is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chi p 8.1 k resistance and the external capaci tor. figure 13. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power le vel reduces the noise spectrum level. table 35. 2.7-v ac operatio nal amplifier specifications symbol description min typ max units t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/s v/s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz ? 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz) nv/rthz 0 0.01 0.1 1.0 10
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 40 of 65 figure 14. typical opamp noise ac low power comparator specifications ta b l e 3 6 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v at 25 c and are for design guidance only. table 36. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s ? 50 mv overdrive comparator reference set within v reflpc 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 41 of 65 ac digital block specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 37. 5-v and 3.3-v ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd ?? 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [25] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [25] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [25] ??ns disable mode 50 [25] ??ns input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the i nput clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [25] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz note 25. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 42 of 65 table 38. 2.7-v ac digital block specifications function description min typ max units notes all functions block input clock frequency ? ? 12.7 mhz 2.4 v < v dd < 3.0 v timer capture pulse width 100 [26] ? ? ns input clock frequency, with or without capture ? ? 12.7 mhz counter enable input pulse width 100 [26] ? ? ns input clock frequency, no enable input ? ? 12.7 mhz input clock frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 [26] ? ? ns disable mode 0 100 [26] ? ? ns input clock frequency ? ? 12.7 mhz crcprs (prs mode) input clock frequency ? ? 12.7 mhz crcprs (crc mode) input clock frequency ? ? 12.7 mhz spim input clock frequency ? ? 6.35 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock frequency ? ? 4.23 mhz width of ss_ negated between transmissions 100 [26] ? ? ns transmitter input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. receiver input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. note 26. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period).
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 43 of 65 ac analog output buffer specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 39. 5-v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/s v/s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/s v/s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 40. 3.3-v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/s v/s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/s v/s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 44 of 65 ac external clock specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 41. 2.7-v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 4 4 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3 3 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.4 0.4 ? ? ? ? v/s v/s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.4 0.4 ? ? ? ? v/s v/s bw ob small signal bandwidth, 20 mv pp , 3db bw, 100 pf load power = low power = high 0.6 0.6 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1 v pp , 3db bw, 100 pf load power = low power = high 180 180 ? ? ? ? khz khz table 42. 5-v ac external clock specifications symbol description min typ max units f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ? ? s notes 27. maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock di vider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 28. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this ca se, the cpu clock divider ensures that the fifty percent duty cycle requirement is met table 43. 3.3-v ac external clock specifications symbol description min typ max units f oscext frequency with cpu clock divide by 1 [27] 0.093 ? 12.3 mhz f oscext frequency with cpu clock divide by 2 or greater [28] 0.186 ? 24.6 mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ? ? s
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 45 of 65 ac programming specifications ta b l e 4 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. notes 29. maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock di vider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 30. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this ca se, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. 31. for the full industrial range, you must employ a temperature sens or user module (flashtemp) and feed the result to the tempe rature argument before writing. refer to the flash apis application note design aids ? reading and writing psoc ? flash ? an2015 for more information. table 44. 2.7-v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 [29] 0.093 ?12.3mhz f oscext frequency with cpu clock divide by 2 or greater [30] 0.186 ?12.3mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ?s table 45. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 20 ? ms t write flash block write time ? 80 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd ? 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? v dd ? 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 ? v dd ? 3.0 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once t program_hot flash block erase + flash block write time ? ? 200 [31] ms 0 c ? tj ? 100 c t program_cold flash block erase + flash block write time ? ? 400 [31] ms ?40 c ? tj ? 0 c
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 46 of 65 ac i 2 c specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. figure 15. definition for timing for fast-/standard-mode on the i 2 c bus table 46. ac characteristics of the i 2 c sda and scl pins for v dd > 3.0 v symbol description standard-mode fast-mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ?0.6 ?s t lowi2c low period of the scl clock 4.7 ?1.3 ?s t highi2c high period of the scl clock 4.0 ?0.6 ?s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ?s t hddati2c data hold time 0 ?0 ?s t sudati2c data setup time 250 ?100 [32] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ?s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ?s t spi2c pulse width of spikes are suppressed by the input filter ? ?0 50ns table 47. ac characteristics of the i 2 c sda and scl pins for v dd ? ? 3.0 v (fast mode not supported) symbol description standard-mode fast-mode units min max min max f scli2c scl clock frequency 0 100 ? ?khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ? ? ?s t lowi2c low period of the scl clock 4.7 ? ? ?s t highi2c high period of the scl clock 4.0 ? ? ?s t sustai2c setup time for a repeated start condition 4.7 ? ? ?s t hddati2c data hold time 0 ? ? ?s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ?s t bufi2c bus free time between a stop and start condition 4.7 ? ? ?s t spi2c pulse width of spikes are suppressed by the input filter ? ? ? ?ns note 32. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t sudat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 47 of 65 packaging information this section illustrates the packaging specifications for the cy 8c24x23a psoc device, along with the thermal impedances for eac h package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip's footprint. fo r a detailed description of the emulation tools' dimensions, see the emulator pod drawings at http://www.cypress.com/design/mr10161 . packaging dimensions figure 16. 8-pin (300-mil) pdip 51-85075 *c
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 48 of 65 figure 17. 8-pin (150-mil) soic figure 18. 20-pin (300-mil) molded dip 51-85066 *e 51-85011 *c
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 49 of 65 figure 19. 20-pin (210-mil) ssop 51-85077 *e
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 50 of 65 figure 20. 20-pin (300-mil) molded soic figure 21. 28-pin (300-mil) molded dip 51-85024 *e 51-85014 *f
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 51 of 65 figure 22. 28-pin (210-mil) ssop figure 23. 28-pin (300-mil) molded soic 51-85079 *e 51-85026 *f
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 52 of 65 figure 24. 32-pin sawn qfn package important note for information on the preferred dimensions for mounting qfn packages, see the application note, application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . figure 25. 56-pin (300-mil) ssop 001-30999 *c 51-85062 *e
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 53 of 65 thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 5 0 shows the solder reflow temperature limits that must not be exceeded. table 48. thermal impedances per package package typical ? ja [33] 8-pin pdip 123 c/w 8-pin soic 185 c/w 20-pin pdip 109 c/w 20-pin ssop 117 c/w 20-pin soic 81 c/w 28-pin pdip 69 c/w 28-pin ssop 101 c/w 28-pin soic 74 c/w 32-pin qfn [34] 22 c/w table 49. typical package capacitance on crystal pins package package capacitance 8-pin pdip 2.8 pf 8-pin soic 2.0 pf 20-pin pdip 3.0 pf 20-pin ssop 2.6 pf 20-pin soic 2.5 pf 28-pin pdip 3.5 pf 28-pin ssop 2.8 pf 28-pin soic 2.7 pf 32-pin qfn 2.0 pf table 50. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 8-pin pdip 260 c 30 seconds 8-pin soic 260 c 30 seconds 20-pin pdip 260 c 30 seconds 20-pin ssop 260 c 30 seconds 20-pin soic 260 c 30 seconds 28-pin pdip 260 c 30 seconds 28-pin ssop 260 c 30 seconds 28-pin soic 260 c 30 seconds 32-pin qfn 260 c 30 seconds notes 33. t j = t a + power ? ja 34. to achieve the thermal impedance specified for the qfn package, refer to application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at www.amkor.com.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 54 of 65 development tool selection this section presents the development tools available for all current psoc device families including the cy8c24x23a family. software psoc designer ? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free ofcharge at http://www.cypress.com. development kits all development kits can be purc hased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface lets you to run, halt, and single step the processor and view the content of specific memory locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit lets you to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a development board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of bread boar ding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 55 of 65 device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industria l case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 51. emulation and programming accessories part number pin package flex-pod kit [35] foot kit [36] adapter [37] all non-qfn all non-qfn cy3250-24x23a cy3250-8dip-fk, cy3250-8soic-fk, cy3250-20dip-fk, cy3250-20soic-fk, cy3250-20ssop-fk, cy3250-28dip-fk, cy3250-28soic-fk, cy3250-28ssop-fk adapters can be found at http://www.emulation.com. notes 35. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 36. foot kit includes surface mount feet that can be soldered to the target pcb. 37. programming adapter converts non-dip package to dip footprint. sp ecific details and ordering information for each of the ada pters can be found at http://www.emulation.com .
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 56 of 65 ordering information the following table lists the cy8c24x23a psoc device?s key package features and ordering codes. note for die sales information, contact a local cypress sales office or field applications engineer (fae). ordering code definitions table 52. cy8c24x23a psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) switch mode pump temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 8-pin (300-mil) dip cy8c24123a-24pxi 4 k 256 no ?40 c to +85 c 4 6 6 4 2 no 8-pin (150-mil) soic CY8C24123A-24SXI 4 k 256 no ?40 c to +85 c 4 6 6 4 2 no 8-pin (150-mil) soic (tape and reel) CY8C24123A-24SXIt 4 k 256 no ?40 c to +85 c 4 6 6 4 2 no 20-pin (300-mil) dip cy8c24223a-24pxi 4 k 256 yes ?40 c to +85 c 4 6 16 8 2 yes 20-pin (210-mil) ssop cy8c24223a-24pvxi 4 k 256 yes ?40 c to +85 c 4 6 16 8 2 yes 20-pin (210-mil) ssop (tape and reel) cy8c24223a-24pvxit 4 k 256 yes ?40 c to +85 c 4 6 16 8 2 yes 20-pin (300-mil) soic cy8c24223a-24sxi 4 k 256 yes ?40 c to +85 c 4 6 16 8 2 yes 20-pin (300-mil) soic (tape and reel) cy8c24223a-24sxit 4 k 256 yes ?40 c to +85 c 4 6 16 8 2 yes 28-pin (300-mil) dip cy8c24423a-24pxi 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 28-pin (210-mil) ssop cy8c24423a-24pvxi 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 28-pin (210-mil) ssop (tape and reel) cy8c24423a-24pvxit 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 28-pin (300-mil) soic cy8c24423a-24sxi 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 28-pin (300-mil) soic (tape and reel) cy8c24423a-24sxit 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 32-pin (5 5 mm 1.00 max) sawn qfn cy8c24423a-24ltxi 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 32-pin (5 5 mm 1.00 max) sawn qfn (tape and reel) cy8c24423a-24ltxit 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes 56-pin ocd ssop cy8c24000a-24pvxi [38] 4 k 256 yes ?40 c to +85 c 4 6 24 10 2 yes note 38. this part may be used for in-circuit debugging. it is not available for production. cy 8 c 24 xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx = qfn pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 57 of 65 acronyms acronyms used ta b l e 5 3 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywu sb6953 psoc? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 (001-17397) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 53. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter ocd on-chip debug api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual-in-line package cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop ct continuous time por power on reset dac digital-to-analog converter ppor precision power on reset dc direct current prs pseudo-random sequence dtmf dual-tone multi-frequency pso c? programmable system-on-chip eco external crystal oscillator pwm pulse width modulator eeprom electrically erasable programmable read-only memory qfn quad flat no leads gpio general purpose i/o rtc real time clock ice in-circuit emulator sar successive approximation ide integrated development environment sc switched capacitor ilo internal low speed oscillator slimo slow imo imo internal main oscillator smp switch mode pump i/o input/output soic small-outline integrated circuit irda infrared data association spi tm serial peripheral interface issp in-system serial programming sram static random access memory lcd liquid crystal display srom supervisory read only memory led light-emitting diode ssop shrink small-outline package lpc low power comparator uart universal asynchronous receiver / transmitter lvd low voltage detect usb universal serial bus mac multiply-accumulate wdt watchdog timer mcu microcontroller unit xres external reset
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 58 of 65 document conventions units of measure ta b l e 5 4 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 54. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes s microsecond db decibels ms millisecond c degree celsius ns nanosecond ff femto farad ps picosecond pf picofarad v microvolts khz kilohertz mv millivolts mhz megahertz mvpp millivolts peak-to-peak rt-hz root hertz nv nanovolts k ? kilohm v volts ? ohm w microwatts a microampere w watt ma milliampere mm millimeter na nanoampere ppm parts per million pa pikoampere % percent mh millihenry glossary active high 5. a logic signal having its asserted state as the logic 1 state. 6. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 59 of 65 bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. glossary (continued)
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 60 of 65 digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technol ogy that provides users with the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. glossary (continued)
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 61 of 65 m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. glossary (continued)
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 62 of 65 rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory . a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged un til it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued)
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 63 of 65 document history page document title: cy8c24123a, cy8c24223a, cy8c24423a psoc ? programmable system-on-chip document number: 38-12028 revision ecn orig. of change submis- sion date description of change ** 236409 sfv see ecn new silicon and new document ? preliminary datasheet. *a 247589 sfv see ecn changed the title to read ?final? datashee t. updated electric al specifications chapter. *b 261711 hmt see ecn input all sfv memo changes. updated electrical specifications chapter. *c 279731 hmt see ecn update electrical specifications chapter , including 2.7 vil dc gpio spec. add solder reflow peak temperature table. clean up pinouts and fine tune wording and format throughout. *d 352614 hmt see ecn add new color and cy logo. add url to preferred dimensions for mounting mlf packages. update transmitter and receiver ac digital block electrical specifi- cations. re-add issp pinout identifier. de lete electrical specification sentence re: devices running at greater than 12 mh z. update solder reflow peak temper- ature table. fix cy.com urls. update cy copyright. *e 424036 hmt see ecn fix smp 8-pin soic error in feature an d order table. update 32-pin qfn e-pad dimensions and rev. *a. add issp note to pinout tables. update typical and recommended storage temperature per industrial specs. add ocd non-production pinout and package di agram. update cy branding and qfn convention. update package diagram revisions. *f 521439 hmt see ecn add low power comparator (lpc) ac/dc electrical spec. tables. add new dev. tool section. add cy8c20x34 to psoc device characteristics table. *g 2256806 uvs/pyrs see ecn added sawn pin information. *h 2425586 dso/aesa see ecn corrected ordering information to include cy8c24423a-24ltxi and cy8c24423a-24ltxit *i 2619935 ogne/ aesa 12/11/2008 changed title to ?cy8c24123a, cy8c24223a, cy8c24423a psoc ? programmable system-on-chip?? updated package diagram 001-30999 to *a. added note on digital signaling in dc analog reference specifications on page 25 . added die sales information note to ordering information on page 56 . *j 2692871 dpt/pyrs 04/16/2009 updated max package thickness for 32-pin qfn package formatted notes updated ?getting started? on page 6 updated ?development tools? on page 6 and ?designing with psoc designer? on page 7 *k 2762168 jvy/ aesa 06/25/2009 updated dc gpio, ac chip-level, and ac programming specifications as follows: modified fimo6 and twri te specifications. replaced t ramp (time) specification with sr power_up (slew rate) specification. added note [9] to flash endurance specification. added ioh, iol, dc ilo , f 32k_u , t powerup , t eraseall , t program_hot , and t program_cold specifications.
cy8c24123a cy8c24223a cy8c24423a document number: 38-12028 rev. *r page 64 of 65 *l 2897881 maxk/njf 03/23/2010 add ?contents? on page 2. update unit in table 10-28 and ta b l e 3 8 of spis maximum input clock frequency from ns to mhz. update revision of package diagrams for 8 pdip, 8 soic, 20 pdip, 20 ssop, 20 soic, 28 pdip, 28 ssop, 28 soic, 32 qfn. updated cypress webs ite links. removed reference to psoc designer 4.4. updated 56-pin ssop def initions and diagram. added t baketemp and t baketime parameters in absolute maximum ratings . updated 5-v dc analog reference specifications table. updated note in packaging information . added note 29. updated solder reflow specifications table. removed third party tools and build a psoc emulator into your board. removed inactive parts from ordering information . update trademark info. and sales, solutions, and legal information . *m 2942375 vmad 06/02/2010 updated content to match cu rrent style guide and datasheet template. no technical updates. *n 3032514 njf 09/17/10 added psoc device characteristics table. added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specificat ion, removed existing jitter specifications. updated analog reference tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac di gital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. updated figure 13 since the labelling for y-axis was incorrect. template and styles update. *o 3098766 yji 12/01/2010 sunset review; no content update *p 3351721 yji 08/31/2011 full annual review of document. no changes are required. *q 3367463 btk/gir 09/22/2011 up dated text under dc analog reference specifications on page 25 . removed package diagram spec 51-85188 as there is no active mpn using this outline drawing. the text ?pin must be left floating? is included under description of nc pin in ta b l e 5 on page 11 and table 6 on page 12 . updated table 50 on page 53 to give more clarity. removed footnote #35. *r 3598291 lure/xzng 04/24/2012 changed the pwm description string from ?8- to 32-bit? to ?8- and 16-bit?. document title: cy8c24123a, cy8c24223a, cy8c24423a psoc ? programmable system-on-chip document number: 38-12028 revision ecn orig. of change submis- sion date description of change
document number: 38-12028 rev. *r revised april 24, 2012 page 65 of 65 psoc designer? is a trademark and psoc? is a registered trademark of cypress semiconductor corporation. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. cy8c24123a cy8c24223a cy8c24423a ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of of fices, solution centers, ma nufacturers? representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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